To provide a data sequence conversion device which needs only a small amount of memory capacity.
A deinterleaver 4 successively designates a read address found, according to a read address =(8 × write address MOD (-1624) +int (8 ×write address/1624) after writing the data code string of a 1st super frame with the same pattern as in the conventional manner in a memory 6, reads a data code from the memory area of the designated address in the first half period of one clock cycle period and writes a data code in the memory area in it latter half period. When there is a memory capacity for one super frame, it is sufficient that for the memory capacity this data sequence conversion device needs only half the memory capacity that is needed in the conventional cases.
YUASA MASATOSHI
FUJINO NORIO
