To enable speed conversion, even when M/N has a fractional part if the number of bits of an unconverted input signal is defined as M and the number of bits of a converted output signal is defined as N.

If the least common multiple between the bit width M of the unconverted input signal and the bit width N of the converted output signal is defined as G, a data write selector 3 writes data by M bits each at a time in a data storage memory 2 with G-bit width while dividing the data into G/M times under the control of a write counter 6, and a data read selector 4 reads the data by N-bits each at a time from the memory 2, while dividing the data into G/N times under the control of a read counter 7.