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Title:
DEVICE FOR MULTIPLEXING DIGITAL SIGNAL
Document Type and Number:
Japanese Patent JPS596620
Kind Code:
A
Abstract:

PURPOSE: To remove waveform distortion from an output by delaying specific output signals from a latch circuit and then supplying the delayed outputs to a multiplexer.

CONSTITUTION: Output signals 00'∼03' from the latch circuit 8 have distortion at the leading and trailing edge parts. The output signals 02', 03 are delayed by about a half of a clock period by a delay circuit 9 and the delayed signals S2', S3 are outputted. At the timing of output signals T0', T1', T2', T3, AND between the signals O0', 01' and S2', S3' is found. At all points between 00', and T0', 01' and T1', S2' and T2', S3' and T3', signals are stabilized without distortion. Therefore, the output signals of AND circuits are stable and an output series signal from an OR circuit 15 has no distortion.


Inventors:
WATANABE YOSHINORI
OONO KENZOU
Application Number:
JP11576182A
Publication Date:
January 13, 1984
Filing Date:
July 02, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03M9/00; H04J3/00; H04J3/04; H04J3/10; (IPC1-7): H04J3/00
Attorney, Agent or Firm:
Toshio Nakao



 
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