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Title:
DEVICE PERFORMING WRITE-IN IN WHICH LOSS OF MRAM IS LESS
Document Type and Number:
Japanese Patent JP3739679
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a device performing write-in in which loss of MRAM is less and in which memory cells having large resistance, short word lines and/or bit lines are not utilized.
SOLUTION: This device has many memory cells (Z0, Z1, etc.), and these memory cells are provided respectively in a memory cell field between a word line(WL) and bit lines (BL, BL0, BL1, etc.). At the time of write-in process for the prescribed memory cell, voltage drop (V1-V2) is caused in the selected word line(WL) connected to this memory cell. When voltage V1 or voltage V2<V1 is applied to both end parts of the selected word line(WL), cell voltage can be made ±(V1-V2)/2 at the maximum by adjusting all bit lines (BL, BL0, BL1, etc.), to voltage (V1+V2)/2.


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Inventors:
Ditmar goggles
Helmut, Kandorf
Lamaz, Stephan
Application Number:
JP2001235533A
Publication Date:
January 25, 2006
Filing Date:
August 02, 2001
Export Citation:
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Assignee:
Infineon Technologies AG
International Classes:
G11C11/14; G11C11/15; G11C5/06; G11C11/16; H01L21/8246; H01L27/105; H01L43/08; (IPC1-7): G11C11/14; G11C11/15; H01L27/105; H01L43/08
Domestic Patent References:
JP2002008368A
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Toru Enya
Ichiro Kaneko