PURPOSE: To provide a pixel synchronizing device capable of optimally sampling even when a sampling pulse is delayed.

CONSTITUTION: An input analog signal is subjected to sample-and-hold by sample-hold circuits 41, 42, 43, and a rectangular wave is formed, and the rectangular wave is supplied to sample/hold parts 21B, 22B in horizontal drivers 21, 22. Then, in timing generator parts 21A, 22A in the horizontal drivers 21, 22, the sampling pulse is formed based on an input pulse, and the rectangular wave is subjected to sample-and-hold again according to the sampling pulse. Then, hold values held by the sample/hold parts 21B, 22B are supplied to a display pannel 3 in line sequentiality.