To provide a device comparing associative memory, a method of controlling the comparing device, and associative memory.
The associative memory cell is a memory cell made of a first transistor T1 for storing data bits and a second transistor T2 for storing the complements of the data bits. Each transistor is formed on a semiconductor-on-insulator substrate; and each transistor has a memory cell including a front control gate and a back control gate BG1, BG2 so as to cut off the transistors, and a comparator circuit applying a nominal read-out voltage to each the front control gate to operate in a read mode; controlling the back control gate BG1, BG2, for one of them by bits (DATA) and the other by the complements (DATAb) of bits; cutting off the pass transistor among them when the bits (DATA) and stored bits agree one another; and checking whether there is a current flowing in the source line SL connected to each source.
PHELAN RICHARD
JPH0773683A | 1995-03-17 | |||
JPH0757479A | 1995-03-03 | |||
JPH05166387A | 1993-07-02 | |||
JP2011081874A | 2011-04-21 | |||
JPH0612884A | 1994-01-21 | |||
JPH05189980A | 1993-07-30 | |||
JP2002260388A | 2002-09-13 | |||
JP2011081874A | 2011-04-21 | |||
JPH0612884A | 1994-01-21 | |||
JPH0773683A | 1995-03-17 | |||
JPH05189980A | 1993-07-30 | |||
JP2002260388A | 2002-09-13 | |||
JPH0757479A | 1995-03-03 | |||
JPH05166387A | 1993-07-02 |
US20060013028A1 | 2006-01-19 | |||
US20060013028A1 | 2006-01-19 | |||
WO2008134688A1 | 2008-11-06 |