メモリデバイスのための装置、メモリデバイスおよびメモリデバイスの制御のための方法

Title:

メモリデバイスのための装置、メモリデバイスおよびメモリデバイスの制御のための方法

Document Type and Number:

Japanese Patent JP5922740

Kind Code:

B2

Abstract:

Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.

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Inventors:

Stanton McDonough Keyler
Margot Anne Lapense

Application Number:

JP2014219123A

Publication Date:

May 24, 2016

Filing Date:

October 28, 2014

Export Citation:

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Assignee:

Seagate Technology LLC

International Classes:

G06F3/06; G06F3/08; G06F13/10

Domestic Patent References:

JP2008152440A
JP2008217855A
JP2012514809A
JP2010044814A
JP2015026263A
JP9258907A

Foreign References:

US20100082879
US20090172249

Attorney, Agent or Firm:

Fukami patent office

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