Title:
集積回路の性能を調整するための装置および方法
Document Type and Number:
Japanese Patent JP2007538474
Kind Code:
A
Abstract:
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
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Inventors:
Louis, david
Betz, bone
Rahim, Ilfan
McClenny, Peter
Liu, You-Juan W.
Pedersen, Bruce
Betz, bone
Rahim, Ilfan
McClenny, Peter
Liu, You-Juan W.
Pedersen, Bruce
Application Number:
JP2007527379A
Publication Date:
December 27, 2007
Filing Date:
May 18, 2005
Export Citation:
Assignee:
Altera Corporation
International Classes:
H03K19/173; G06F17/50; H01L21/82; H01L21/822; H01L27/04; H03K5/13; H03K19/00; H03K19/003; H03K19/094; H03K5/00
Domestic Patent References:
| JPH05108194A | 1993-04-30 | |||
| JPH04247653A | 1992-09-03 | |||
| JPS61160960A | 1986-07-21 | |||
| JP2000101416A | 2000-04-07 | |||
| JP2001345693A | 2001-12-14 | |||
| JP2001156261A | 2001-06-08 | |||
| JP2003168735A | 2003-06-13 | |||
| JP2003110028A | 2003-04-11 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita