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Title:
集積回路の回路構成要素にクロックを分配する装置および方法
Document Type and Number:
Japanese Patent JP4015706
Kind Code:
B2
Abstract:
A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.

Inventors:
Ken El Wong
Keiri Jay Fitzpatrick
Jeffrey E. Smith
Application Number:
JP15552994A
Publication Date:
November 28, 2007
Filing Date:
June 15, 1994
Export Citation:
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Assignee:
INTEL CORPORATION
International Classes:
G06F1/10; G06F1/32; H01L21/82; H01L21/822; H01L27/04; H03K5/15
Domestic Patent References:
JP2208956A
JP5136380A
JP3190262A
JP561564A
JP60111521A
JP1169522A
JP6425626A
JP4274358A
JP4373160A
JP5150870A
JP774256A
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Shigeki Yamakawa



 
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