PURPOSE: To evaluate the propriety of parity checkers, to reduce the number of the steps of a micro instruction and to improve a processing ability by suppressing an interruption to the micro instruction due to a parity error, and simultaneously, suppressing the hold of an error register.

CONSTITUTION: An error neglect flip-flop 11 is set to 1 by the micro instruction, the interruption is suppressed by a micro instruction sequence control signal 14, and an error register 10 is prevented from being held. The data, in which a parity is correct, are stored into registers 2, 4, 6 and 8, the parity is checked, and when a bit which is not 0 exists after reading the error register 10, the parity checker corresponding to the bit is considered to be in trouble. Thereafter, the data, in which the parity is in error, are stored into the registers 2, 4, 6 and 8, the parity is checked, and the parity checker corresponding to the bit which is not 1 after reading the error register 10 is considered to be in trouble. Thus, the propriety of the parity checkers can be evaluated, and the steps of the micro instruction can be reduced.