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Title:
ANALYZER AND METHOD FOR ANALYZING FAILURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3157674
Kind Code:
B2
Abstract:

PURPOSE: To obtain a potential failure image of semiconductor integrated circuit (LSI) in real time and shorten failure analysis time by regularly alternately outputting a potential distribution image of a good product or a good product condition and another potential distribution image of inferior product or inferior product conduction.
CONSTITUTION: An image of any part of the whole face of LSI can be obtained at a real time by regularly alternately outputting a potential distribution image of a good product or a good product condition and another potential distribution image of an inferior product or an inferior product condition. The lefthand side of a figure indicates good product condition setting, and the righthand side thereof shows a case where respective test conditions are set in inferior product condition setting. In order from above, a test vector, a clock for operating LSI, an image taken-in gate signal of a beam source of an electron beam (EB) tester and a potential distribution image made from a high speed potential distribution learning method (CCFI method) are shown. The lefthand CCFI potential distribution image indicates a distribution image (good product image in the good condition, and the righthand CGFI potential distribution image shows another distribution image (inferior product image) in the inferior product conditions.


Inventors:
Toyokazu Nakamura
Yasuko Hanagama
Toru Tsujide
Kenji Morohashi
Application Number:
JP67294A
Publication Date:
April 16, 2001
Filing Date:
January 10, 1994
Export Citation:
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Assignee:
NEC
Schlumberger Co., Ltd.
International Classes:
G01R31/319; H01L21/66; G01R31/302; (IPC1-7): G01R31/302; H01L21/66
Domestic Patent References:
JP5256917A
JP545423A
JP6270774A
JP2194541A
JP1277781A
JP6217132U
Attorney, Agent or Firm:
Yoshiyuki Iwasa