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Patent Searching and Data


Title:
DIFFERENTIAL AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JPS62226713
Kind Code:
A
Abstract:

PURPOSE: To reduce the current consumption and wiring capacitance and to prevent adverse effect attended with the fluctuation of a power voltage by adopting a depletion MOS transistor (TR) having a gate held at a ground potential for the lst MOS TR and outputting an output signal to an input signal with respect to a threshold voltage of the said TR.

CONSTITUTION: In the depletion MOS 32, a drain current flows with a gate voltage zero and the gate voltage is connected to ground, then the current supply capability I depends on the control of a threshold voltage Vtd or the dimension W/L of the depletion MOS 32 as shown in the following equation: I=(W/L × 1/2)Vtd2. Through the constitution above, when an input address signal Ain is at an H level, the current supply capacity of the MOS 32 is lower than that of a MOS 31, aud when at an L level, it is kept higher than that of the MOS31. Thus, the absolute value of a threshold voltage Vtd of the MOS 32 is selected between the H and L level of the input address signal Ain. That is, the threshold voltage Vtd of the MOS 32 is used as the reference voltage to eliminate a conventional reference voltage generating circuit 13.


Inventors:
HONDA TAKASHI
MIYAMOTO SANPEI
Application Number:
JP6949286A
Publication Date:
October 05, 1987
Filing Date:
March 27, 1986
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H03K5/02; H03F3/45; (IPC1-7): H03F3/45; H03K5/02
Attorney, Agent or Firm:
Kakimoto Kyosei