Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
DIFFERENTIAL TYPE LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH02228128
Kind Code:
A
Abstract:

PURPOSE: To realize various logical functions by only changing one piece of mask pattern by realizing various logical functions with only the same cell by whether an ion implantation is executed to the 4-channel part of an N chan nel type MOSFET or not.

CONSTITUTION: A cell is constituted by using a circuit where four lines of FETs connected in series with two pieces of N channel type MOSFETs are provided and the drain electrodes of two adjacent FET lines make in common and are connected to a load MOSFET, and also, the source electrodes of odd numbered and even numbered FET lines make in common respectively and are connected to a pair of third N channel type MOSFETs as a fundamental logic circuit. This cell is arranged like a matrix on a semiconductor chip, and the N channel type MOSFET is changed selectively to a depression type MOSFET or an enhancement type MOSFET. In such a manner, by whether an ion implantation is executed to a channel part or not, various logical functions can be realized with only the same cell.


Inventors:
MORIUCHI HISAHIRO
Application Number:
JP4650489A
Publication Date:
September 11, 1990
Filing Date:
March 01, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H03K19/173; H03K19/0944; H03K19/21; (IPC1-7): H03K19/0944; H03K19/173; H03K19/21
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
Previous Patent: LOGIC CIRCUIT

Next Patent: PULSE COUNTER CIRCUIT