To effectively utilize the number of transmission channels and further to enable a viewer to easily grasp or select a program by storing reduced digital image data in the storage area of a memory and displaying the stored contents of the memory on a screen.

An MPEG video coder 15 selects prescribed digital picture data from a received data stream and executes decode processing. An OSD circuit 23 executes reduction processing to the digital picture data outputted from the MPEG video coder 15, so as to horizontally or vertically reduce them on the display screen. A CPU 19 stores the digital picture data outputted from this OSD circuit 23 at a position, corresponding to a position for display on the screen in a RAM 22 having a storage area corresponding to the display screen. Then, the reduced digital picture data are stored in the storage area of the RAM 22, and the stored contents of the RAM 22 are displayed on a CRT monitor 26.