PURPOSE: To attain a high-speed bus cycle by selectively omitting an error correction function based on the data update rate.

CONSTITUTION: A digital circuit having a memory 5 with an error correction circuit is provided with an address area directive register 3 presetting the address in an error correction/omission area, address identification section 4 comparing the value with each memory access address, bus control section 2 controlling the bus cycle, and parity check circuit for checking parity at the time of correcting and omitting errors. By making the bus cycle of the memory access variable, the error correction is performed only on the access in the specific area of the memory and the parity check is performed only on the other areas.