PURPOSE: To provide the clock multiplying circuit which multiplies the frequency of an input clock signal with simple circuit configuration.

CONSTITUTION: This circuit is provided with a buffer logic 11 for delay serially connecting buffers 11a-11e provided with the delay characteristics of signal propagation. When an input clock signal (a) is inputted from an input terminal 10, a delayed clock (b) is generated. When this signal and the input clock signal (a) are exclusively ORed by an EOR 12 and the output is dispatched to an LPF 13, a sine wave signal double multiplying the frequency is generated. When the waveform of this signal is shaped by a buffer 16, a clock signal (e) multiplying the frequency is provided.