To provide a digital-control-type phase-composing circuit system capable of improving jitter resistance and expanding the lock range.

The digital-control phase-composing circuit system has: a phase-composing circuit which is supplied with two input clock signals having a phase difference between them and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal; a binary phase comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal; a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value; and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as the control signal.