Title:
DIGITAL DEMODULATION CIRCUIT
Document Type and Number:
Japanese Patent JP3496860
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize the digital demodulation circuit that detects a carrier frequency error with high accuracy even when a carrier frequency error is large and compensates the error.
SOLUTION: A plurality of paths are provided through which a different fixed value &phiv off is added to a phase rotation signal a9 denoting a carrier frequency error in a delay detection signal and averaging is conducted in each path after a modulo arithmetic operation. Then the fixed value &phiv off is subtracted from the mean value of each path to obtain carrier frequency errors a21-1, a21-2, a21-3. Then the carrier frequency errors for each path are selected or combined to detect a carrier frequency error a10 with high accuracy.
More Like This:
| JPS6128260 | CARRIER WAVE SIGNAL DETECTING CIRCUIT |
| JP6600187 | Communication device |
| JPS59152853 | [Title of the device] Phase decision circuit |
Inventors:
Takeshi Onizawa
Kiyoshi Kobayashi
Kiyoshi Kobayashi
Application Number:
JP1834097A
Publication Date:
February 16, 2004
Filing Date:
January 31, 1997
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H04L27/227; (IPC1-7): H04L27/227
Domestic Patent References:
| JP7183925A |
Attorney, Agent or Firm:
Furuya Fumio
Previous Patent: PRODUCTION OF ULTRAFINE ZINC OXIDE
Next Patent: WEFT STORING APPARATUS FOR FLUID JETTING TYPE WEAVING MACHINE
Next Patent: WEFT STORING APPARATUS FOR FLUID JETTING TYPE WEAVING MACHINE