PURPOSE: To obtain the digital filter in which no malfunction due to a level fluctuation of an-input signal is not caused and no consideration as to a line drive capability at an output side is taken.

CONSTITUTION: While an input signal DATA is stored in an n-bit shift capacity shift register 1 for a clock CLK period by a shift clock CLK, it is detected that a parallel Q output and a parallel the inverse of Q output are all logical '1', an RS flip-flop 4 is subject to set/reset control by detection outputs of the AND gates 2, 3, and an output OUT subject to digital filtering processing is obtained from a Q output of the RS flip-flop 4.