Title:
DIGITAL GRAPHIC EQUALIZER
Document Type and Number:
Japanese Patent JP3308055
Kind Code:
B2
Abstract:
PURPOSE: To make the curves of boost characteristics and cut characteristics vertically symmetrical by adding an input signal at the time of boosting or an output signal at the time of cutting to the input signal after passing it through a band-pass filter, and obtaining the respective characteristics.
CONSTITUTION: When the boosting process is started, the input signal X is sent to an adder 2 and respective band-pass filters I1-In through a multiplier 10. The signal X sent to the filters I1-In is sent to an adder 7 through a multiplier 6, delayed by delay elements 51 and 52, and fed back to the adder 7 through multipliers 63 and 64. The output of the adder 2 is delayed by the delay elements 51 and 52 and sent to the adder 7 through the multipliers 63 and 64. Here, the adder 2 adds the output of the adder 7 to the input signal X and outputs an output signal Y. At the time of the cutting, the output signal Y is supplied to the filters I1-In through a feedback loop 32 and inverted in phase by the multiplier 6. Then the curves of the boost characteristics and cut characteristics become vertically symmetrical and deterioration in S/N ratio is reduced.
Inventors:
Hisashi Kihara
Hidekazu Mori
Akira Kanagawa
Atsushi Makino
Shinya Honjo
Masayuki Kato
Hidekazu Mori
Akira Kanagawa
Atsushi Makino
Shinya Honjo
Masayuki Kato
Application Number:
JP20914693A
Publication Date:
July 29, 2002
Filing Date:
August 24, 1993
Export Citation:
Assignee:
Pioneer Corporation
International Classes:
H03H15/00; H03G5/00; H03G5/02; H03H17/02; H03H17/04; H03H21/00; H04B3/04; (IPC1-7): H03H17/02; H03G5/02
Domestic Patent References:
| JP5152897A | ||||
| JP63224513A | ||||
| JP63148708A | ||||
| JP5666918A |
Attorney, Agent or Firm:
Hideo Takino (1 outside)