To provide a digital modulation circuit that selects the sampling frequency of a digital/analog(D/A) converter, asynchronously with and different from a sampling frequency of a digital signal processor(DSP) of the digital modulation circuit with a standardized symbol frequency and an outputs a modulation wave with a desired symbol frequency, without causing timing deviation of a data clock.

A memory 4 is provided to an output of an adder 32 in a DSP in this modulation circuit, an FIFO circuit 6 is placed between an output of the memory 4 and a D/A converter 7, the FIFO circuit 6 temporarily stores a modulation signal outputted from the memory 4 which receives the output of the adder 32 at a sampling rate of the DSP, and outputs the signal with a clock frequency different from that of the DSP to the D/A converter 7 by means of DMA transfer.