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Title:
DIGITAL PHASE LOCKED LOOP CIRCUIT
Document Type and Number:
Japanese Patent JPS63267014
Kind Code:
A
Abstract:

PURPOSE: To improve the general-purpose application by setting switchingly a count bit number of a phase control counter.

CONSTITUTION: A phase control counter 1 is constituted by providing a synchronous counter having flip-flop circuits whose number corresponds to the number of maximum count bits and which is set programmably as a major component and a gate means enabling a carrier forcibly to a carry to each flip-flop circuit of the post-stage in place of an output of the pre-stage, and the phase control of the output of the phase control counter 1 is applied through a lock time control circuit 4 executing the phase control when the degree of the shift of phase exceeds the threshold value based on the result of comparison by a phase comparator circuit 3. Thus, the degree of roughness or the maximum operating speed for the phase control is varied by controlling a gate means of the phase control counter 1 and the lock time of the phase control operation is controlled variably in response to the threshold value set to the circuit 4. Thus, the general-purpose application is improved remarkably.


Inventors:
UEDA MASARU
KITAMURA NOBUAKI
Application Number:
JP9986287A
Publication Date:
November 04, 1988
Filing Date:
April 24, 1987
Export Citation:
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Assignee:
HITACHI LTD
HITACHI VLSI ENG
International Classes:
H03L7/06; (IPC1-7): H03L7/06
Domestic Patent References:
JPS6273819A1987-04-04
JPS61248635A1986-11-05
Attorney, Agent or Firm:
Tomio Dainichi



 
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