To provide an enhanced system that employs a digital phase locked loop.

The system has a digital phase locked loop(PLL) consisting of a full digital circuit configuration and a standard cell structure. The digital PLL has a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including digital chains, a non-glitch MUX and a phase accumulator. The digital phase detector is electrically coupled with the digital frequency synthesizer and supplies digital code information denoting a phase error between the edge of an input reference signal and the edge of a synthesized signal by comparing the edge of the input reference signal with the edge of the synthesized signal.