Title:
DIGITAL PHASE-LOCKING LOOP CIRCUIT
Document Type and Number:
Japanese Patent JPS62145924
Kind Code:
A
Abstract:
The digital phase-locked loop circuit extracts the clock signal from a serial flow of coded data by operating so as to determine the phase of the received signal and comparing this phase with that of a locally-generated signal.The error signal obtained from the comparison is digitally filtered and used to correct the phase of local signal.Besides it is stored and used to effect corrections even in absence of the data flow at the input or in presence of a long zero sequences.
More Like This:
Inventors:
KARURO MOGABUERO BURUNO
RENATO AMUBUROSHIO
RENATO AMUBUROSHIO
Application Number:
JP29685686A
Publication Date:
June 30, 1987
Filing Date:
December 15, 1986
Export Citation:
Assignee:
CSELT CENTRO STUDI LAB TELECOM
International Classes:
H03L7/06; H04L7/033; (IPC1-7): H03L7/06; H04L7/02
Attorney, Agent or Firm:
Kazuho Kawarada