To secure the high frequency stability even when no reference input signal is supplied any more from a GPS and a free-running state is set by preparing an equalization processing means and a sequential equalization processing means and controlling a VCXO(voltage controlled oscillator) based on the sequential equalization value of the control voltage when the input of the reference input signal is discontinued.

A CPU 11 of this DPPLL(digital processing PLL) has an equalization processing part 13 which equalizes the phase difference of a phase comparator 1 and a sequential equalization processing part 15 which sequentially equalizes the control voltage VCONT of a VCXO 7. The voltage VCONT which varies according to the variance of phase difference that is equalized and suppressed at the part 13 is sequentially equalized at the part 15 and the sequential equalization value is outputted. Thus, the VCXO 7 is controlled by the sequential equalization value when the input of a reference input signal is discontinued and a free-running state is set.