Title:
DIGITAL SAMPLING METHOD IN SYNCHRONISM WITH SYSTEMATIC FREQUENCY
Document Type and Number:
Japanese Patent JP3282187
Kind Code:
B2
Abstract:
PURPOSE: To provide a digital sampling method in synchronism with systematic frequency capable of obtaining sampling signals enabling one cycle to be divided equally.
CONSTITUTION: Frequency of a one cycle period standard oscillator 6 in systematic input is counted by means of a one cycle counter 5, and a value which is obtained by cancelling by (m) bits in one cycle frequency obtained by latching this count value by means of a frequency latch circuit 7 is inputted to an updown counter 22 in a digital PLL circuit 20. This output is reloaded synchronously onto a base counter 23, and sampling signals to divide one cycle equally into 2m are outputted from the base counter 23, and the output of the base counter 23 is divided by means of a 2m dividing circuit 24, and by comparing a phase of systematic frequency (fin) and a phase of self advancing frequency (VDPff) from the dividing circuit 24 with each other by means of a phase comparison circuit 25, the updown counter 22 is controlled, so that synchronism in the sampling signals can be obtained.
Inventors:
Toshiyuki Okitsu
Shusaku Umeda
Shusaku Umeda
Application Number:
JP17084291A
Publication Date:
May 13, 2002
Filing Date:
July 11, 1991
Export Citation:
Assignee:
KABUSHIKI KAISHA MEIDENSHA
International Classes:
B60R16/02; G01R19/00; G05B21/02; H02H3/00; H02H3/02; (IPC1-7): G01R19/00
Domestic Patent References:
| JP6073368A | ||||
| JP2212775A | ||||
| JP1267464A | ||||
| JP1191065A | ||||
| JP63111723A | ||||
| JP5546660A | ||||
| JP6018079A | ||||
| JP1235055A | ||||
| JP6412810A | ||||
| JP1261927A | ||||
| JP62163911A | ||||
| JP50157849A | ||||
| JP2312408A | ||||
| JP1138108U | ||||
| JP5741694B2 |
Attorney, Agent or Firm:
Fujiya Shiga (1 person outside)