PURPOSE: To restore the operating state of a circuit by itself when the temporarily interrupted supply of a synchronizing pulse signal is re-started by constituting the circuit so that a counter is reset also by the synchronizing pulse signal besides an inputted master reset signal and a reset signal a decoder generates.

CONSTITUTION: The digital signal circuit is provided with a circuit 50 for timing adjustment which inputs the synchronizing pulse signal and a clock signal and outputs the rest signal synchronizing with the synchronizing pulse signal at specified intervals. The output of this timing adjustment circuit 50 is connected to another input w4 of an OR gate 21. Accordingly, in this circuit, the counter 30 can be reset by three kinds of the reset signals of the master reset signal, the reset signal the decoder 40 outputs, and the reset signal the timing adjustment circuit 50 outputs. Accordingly, even if difference is caused in relation between the phases of the synchronizing pulse signal and data output because of the occurrence of some fault, when the synchronizing pulse signal is supplied, the difference of the relation between the phases of the counter and the synchronizing pulse signal is eliminated periodically, and the counter can be self-reset into its normal operation.