PURPOSE: To provide an attenuation function without complicating the circuit constitution of a parallel serial conversion circuit, by the constitution that a serial output and a parallel output of a shift register are extracted through a switching circuit.

CONSTITUTION: Shift registers 13, 14 of parallel input and serial output to which a part of parallel data is applied from an AD converter 2, and a shift register 15 of parallel input and parallel output to which the rest of the parallel data from the said AD converter is applied, are provided. A Load signal and a clock signal to fetch the parallel data from the AD converter to the shift registers 13, 14 and 15 are inputted to a Load input and a clock input of the shift registers 13, 14 and 15, and the serial data are extracted at an output 17 depending on the switching state of a switching circuit 16. The attenuation up to -24dB is attained with the switching of the switching circuit 16.