Title:
DIGITAL SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH02193362
Kind Code:
A
Abstract:
PURPOSE:To evaluate the effect onto accurate jitter by generating a bit clock having a jitter whose variance is close to the Gaussian distribution from a bit clock without jitter. CONSTITUTION:A digital input signal fed to a serial/parallel converter 10 is converted by the converter 10 in the timing of an 8-bit clock by a serial digital signal of a pattern of an integral number of multiple of the bit clock without jitter and written in a RAM 11 with the bit clock without jitter. A data read from the RAM 11 is converted into a serial digital signal by a parallel/serial converter 12. However, the parallel data subject to parallel/serial conversion is converted for each of 8-bit clock attended with the bit clock having jitter and the converted serial digital signal is converted into the serial digital signal having jitter whose variance is close to the Gaussian distribution attended from the Gaussian node from a Gaussian distribution noise generator A. Thus, the effect of jitter onto an electric circuit section is accurately evaluated.
Inventors:
UWAKAWA YOJI
Application Number:
JP1100789A
Publication Date:
July 31, 1990
Filing Date:
January 21, 1989
Export Citation:
Assignee:
KENWOOD CORP
International Classes:
G11B20/10; H03K3/84; H03M9/00; (IPC1-7): G11B20/10; H03K3/84; H03M9/00
Attorney, Agent or Firm:
Nobuo Sunako (1 outside)