Title:
DIGITAL SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPH01141490
Kind Code:
A
Abstract:
PURPOSE:To previously prevent a return signal harmful to a digital output signal from being mixed by executing oversampling, restricting a band, thereafter, executing necessary signal processing, and suppressing the return signal. CONSTITUTION:The title circuit is equipped with an interpolating circuit 2 outputting a digital signal SV2 by interpolation arithmetic processing of a digital input signal SV, a filter circuit 6 to suppress return signals SL2-SL5 of higher harmonic signals S2-S5 with respect to the digital signal SV2 obtained through a signal processing circuit 5, and a thinning-out circuit 7 sampling a digital signal SY1 outputted from the filter circuit 6 by a prescribed timing and outputting a digital signal SY composed of a necessary sampling frequency fS2. By setting the sampling frequency fS2 at a frequency higher by a prescribed multiple, only the return signals SL2-SL5 of the higher harmonic signals S2-S5 can be easily suppressed, and the return signals SL2-SL5 can avoid being mixed into the outputted digital signal SY.
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Inventors:
MORIWAKE KATSUAKI
Application Number:
JP30036987A
Publication Date:
June 02, 1989
Filing Date:
November 27, 1987
Export Citation:
Assignee:
SONY CORP
International Classes:
H04N9/78; (IPC1-7): H04N9/78
Attorney, Agent or Firm:
Kei Tanabe