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Title:
DIGITAL SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPS59181758
Kind Code:
A
Abstract:

PURPOSE: To reduce signal distortion generated by the variation of a pulse width in case of receiving a digital signal by connecting two comparators having the almost same switching speed so as to execute an inverting operation each other.

CONSTITUTION: A digital signal from a line 11 is applied to comparators 13, 14 after its level is adjusted by a pre-amplifier 12. A signal for determining a discriminating level Vth is applied to the comparators 13, 14 from a discriminating level setting circuit 15. The comparators 13, 14 have the same switching speed, and have such a relation as a logical state of an output is inverted each other. That is to say, a non-inversion input and an inversion input of the comparator 13 are connected to an inversion input and a non-inversion input of the other comparator 14, respectively. Outputs from the comparators 13, 14 are provided to a flip-flop 16. The flip-flop 16 consists of two NAND gates 17, 18. The output from the comparator 13 is provided to the NAND gate 17 as a reset input S through a line 19.


Inventors:
YAMASHITA KOUJI
FUJII YASUHIRO
OKAMOTO KUNINORI
Application Number:
JP4387883A
Publication Date:
October 16, 1984
Filing Date:
March 15, 1983
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H04L25/03; H03K5/01; H04L25/06; (IPC1-7): H03K5/08; H04L25/03
Attorney, Agent or Firm:
Nishikyo Keiichiro



 
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