Title:
DIGITAL SIGNAL PROCESSING DEVICE AND METHOD
Document Type and Number:
Japanese Patent JP3318823
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress the noises which are generated when the switching is carried out between an original sigma delta modulation signal and the signal that undergone the second sigma delta modulation.
SOLUTION: A delay line 3 delays an original ΣΔ (sigma delta) modulation signal by a prescribed number of samples. A ΣΔ modulator 6 outputs a second ΣΔmodulation signal, and a bit length converter 5 sets the modulation signal at the amplitude level of the feedback signal that is applied to an integrator of the first stage used by the modulator 6. Then a digital signal processor 27 receives a switch control signal SD from a control signal input terminal 7 and detects the coincidence of patterns between an original 1-but delay signal SA and a 1-bit signal SB of the second ΣΔ modulation via a pattern coincidence detector 28 to produce a detection signal ST. Thus, a switch controller 29 controls the switching of a changeover switch 4 and outputs a signal that is switched to the signal SB from the signal SA through an output terminal 8.
Inventors:
Masayoshi Noguchi
Hajime Ichimura
Hajime Ichimura
Application Number:
JP17690196A
Publication Date:
August 26, 2002
Filing Date:
July 05, 1996
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11B20/02; H03G3/34; H03M7/00; H03M3/02; H03M7/34; H03M7/50; (IPC1-7): H03M3/02; G11B20/02; H03G3/34
Domestic Patent References:
| JP555924A | ||||
| JP5236388A | ||||
| JP5244010A | ||||
| JP5276048A | ||||
| JP7297646A | ||||
| JP7312022A |
Attorney, Agent or Firm:
Akira Koike (2 outside)