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Patent Searching and Data


Title:
DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP2001092778
Kind Code:
A
Abstract:

To execute processing by a processor during data input/output.

A processor 111 fetches the data from an input buffer memory 112, performs an arithmetic processing by a specified program and outputs the resultant data to an output buffer memory 113. Both of the input buffer memory 112 and the output buffer memory 113 have a double-buffer structure, each of them has areas A, B and holds input/output data for the processor 111. Reading, writing of the input buffer memory 112 and output buffer memory 113 are controlled by a DMA 114 according to the processing state of the processor 111 and the data input/output is performed even during the arithmetic processing of the processor 111.


Inventors:
YOSHIE SHIGEO
NAKADA AKIYOSHI
Application Number:
JP26554499A
Publication Date:
April 06, 2001
Filing Date:
September 20, 1999
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F13/38; G06F5/06; G06F5/16; (IPC1-7): G06F13/38; G06F5/06
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)