To perform high-speed operation with low power consumption by forming a segment bus in a plurality of digital signal processors and controlling the segment bus.

The systolic array digital signal processor has a plurality of core processors arranged in the form of an array, a gateway provided in the core processors to control input-output of data, the segment bus for transferring data in a particular area comprising the plurality of arranged core processors and the gateway, and a control part for controlling the gateway to transfer data between the core processors through the segment bus, to thereby perform high-speed operation at a low clock speed with low power consumption.