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Patent Searching and Data


Title:
DIGITAL SIGNAL RECORDER
Document Type and Number:
Japanese Patent JPH11185400
Kind Code:
A
Abstract:

To easily detect the erroneous data of a sync block by detecting the error of the sync block at a digital data communication time, replacing the data showing the state of the data of the sync block to a value showing the error and recording it.

The inputted digital dubbing data 10 whose a transmission format is loosened by a data receiving circuit 12, and are written in an address of a memory 13 specified by a memory control circuit 14 in sync block. The data written in sync block are read out from the memory 13 in the outer direction. A STATUS replacement circuit 25 refers to a flag in an inner flag memory 24 answering to a STATUS read out from the memory 13, and when it is '0', the circuit 25 replaces the value of the STATUS to the value that the error exists in the sync block as '1111', and when '1', the circuit 25 sends the value of the STATUS to an outer correction encoding circuit 15 without replacing.


Inventors:
KOHAMA TAKANORI
KUBO MASAFUMI
NAGAO AKIYOSHI
SHIMIZU FUTOSHI
Application Number:
JP35704497A
Publication Date:
July 09, 1999
Filing Date:
December 25, 1997
Export Citation:
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Assignee:
SHARP KK
International Classes:
G11B20/18; (IPC1-7): G11B20/18; G11B20/18
Attorney, Agent or Firm:
Takano Akinori