To attain the variable speed reproduction of the digitally, compressed image signals by outputting the time information on the reproduced data after correcting the information.

The time information on the reproduced data is corrected and outputted. This device performs the same processing as that of a normal reproduction mode and outputs the data based on the time information added to the high variable speed reproduction data in a high variable speed reproduction mode and on the corrected time information in a low variable speed reproduction mode respectively. A data selection circuit of this device includes a packet data distribution circuit 411, a storage circuit 412, a time information correction circuit 417 and a switch circuit 414. In a low variable speed reproduction mode, the circuit 417 corrects the time information in response to the rates at which the program clock reference information and the decoding time information needed for decoding the picture data included in the video signals and for managing the display timing are outputted respectively.