PURPOSE: To improve a detecting rate of a sub-code by reproducing sub-codes respectively according to a track reference signal in reproducing at an ordinary speed, and according to recording finish timing of a digital signal in a search mode.
CONSTITUTION: In reproducing at an ordinary speed, a selecting circuit 12 selects a PCM area finish signal 34 generated in an area generating circuit 11 by a mode switching signal from a mode switching signal input terminal 15, and outputs it to a VSC timing generation circuit 13. A circuit 13 generates a VSC start signal 33 with timing of 1.1H by the output from the circuit 12. Since a signal 33 can be always and constantly generated, a sub-code can be stably reproduced. In search mode, the circuit 12 selects an address area finish signal 40 generated in a block address counter 10 and outputs it to a circuit 13. The circuit 13 generates the signal 33 with timing of 1.1H in the same way as reproducing at an ordinary speed.
NAGAI YUTAKA
KIMURA IZUMI
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