PURPOSE: To obtain a synchronizer in which instability for synchronizing a digital signal by AC is avoided by providing a first counter for generating a total count, second counter for conducting second count sequence and a latched circuit.

CONSTITUTION: A first counter 34 responds to a preset line pulse on a line 36 to preset and start first count sequence at a predetermined phase point. A latched circuit 44 is useful as dividing means for receiving only a bit from a selected upper part 48 of the counter 34 and dividing clock value by a selected integer '1'. Further, a second counter 54 sends to a decoder 66 via a bus 64. The decoder 66 senses the time when complete countdown to '1' is performed, and generates an achievement signal on a line 68. If next line pulse arrives at a line 56, the counter 54 is reset, and continued counted number is received by the but 52 from the latch 44.