PURPOSE: To reduce the number of hardwares and signal lines by providing a latch circuit, which holds a previous value stored in a storing circuit in order to stably write an arithmetic result from an arithmetic circuit to the storing circuit, and a circuit to integrate the arithmetic result from the arithmetic circuit on the storing circuit and to output the arithmetic result multiply in time-division or at arbitrarily designated timing.

CONSTITUTION: When '1' is inputted to an input terminal 117, the output of a NAND gate 104 is selected by an AND gate 106. Since the output of the NAND gate 104 is '1' in any condition excepting for the condition of Q0=Q1=1, a computing element 103 adds '1' to the values of the Q0 and Q1 until the condition of the Q0=Q1=1 is obtained. Such adding values S0 and S1 are written through three-state buffers 111 and 112 to a memory 115 at timing to be designated by an R signal of a timing output circuit 101. While the values are written to the memory, the previous value stored in the memory 115 is held in a latch circuit 102 at timing to be designated by the '0' of the timing output circuit 101 so that the values can not be changed.