To preclude malfunction, even if a signal input includes a noise inputted before or after the clock input and remove the noise by providing stages of flip-flops, using a high frequency for their fetches, and making a majority decision to detect a level.

Five D-type flip-flops operate with a clock signal 11. A majority decision arithmetic circuit 6 outputs a level 1 as an output signal 17, when ≥3 of output signals 12 to 16 have the level 1 and a level 0, when not. An output signal 19 is updated each time a retiming signal 18 is inputted. An input signal 9 varies in common timing or does not vary. Therefore, an output signal 19, which does not vary in the duty width of the input signal 9, is obtained. A counter 7 obtains the retiming signal 18 by dividing the frequency of the clock signal 11 by five, but is applied with a reset signal 10 as well to correct the level 0.