Title:
DIRECT MEMORY ACCESS CONTROLLER
Document Type and Number:
Japanese Patent JPS573127
Kind Code:
A
Abstract:
PURPOSE: To control a direct memory access cycle time, by providing a weight number register and a weight counter.
CONSTITUTION: When a DMA controller 1 receives a DMA request signal from each input/output adapter 9, a channel controller 3 of the input/output adapter 9 which is peritted to occupy a common bus 5 is determined by a priority level determining circuit 16. At this time, a DMA channel selecting signal is outputted from a bus controller 17. An initial value set instruction from a weight number resister 2 of the selected channel controller 3 to a weight counter 4 is executed, and the weight counter 4 is set.
Inventors:
FUJII YUTAKA
Application Number:
JP7614180A
Publication Date:
January 08, 1982
Filing Date:
June 05, 1980
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F13/28; (IPC1-7): G06F3/00; G06F13/00
Next Patent: CHINESE CHARACTER INPUT AND OUTPUT DEVICE