Title:
DISCRIMINATION CIRCUIT FOR ADDITIONAL INFORMATION TO VIDEO SIGNAL
Document Type and Number:
Japanese Patent JP3257016
Kind Code:
B2
Abstract:
PURPOSE: To prevent VITS or the like from being erroneous discriminated from additional information.
CONSTITUTION: A signal from a clamp circuit 2 is fed to a low pass filter 6 and the signal from the low pass filter 6 is fed to 1st and 2nd comparator circuits 7a, 7b. Moreover, a 1st threshold level equivalent to, e.g., 45IRE from a DC voltage source 8a is fed to the comparator circuit 7a and the comparison output is fed to a latch circuit 9a. Moreover, a 2nd threshold level equivalent to, e.g. 145IRE from a DC voltage source 8b is fed to the comparator circuit 7b. Then comparison outputs of the 1st and 2nd comparator circuits 7a, 7b are fed to a NOR circuit 20 and a signal from the NOR circuit 20 is fed to a latch circuit 9b. The signal from the latch circuit 9b is fed to an AND circuit 18. Thus, when a signal whose level is an intermediate level is extracted, the write of a buffer memory 17 is inhibited to prevent erroneous discrimination of VITS or the like from additional information.
Inventors:
江▲崎▼ 正
Hirokazu Nagasawa
Morio Ishii
Hirokazu Nagasawa
Morio Ishii
Application Number:
JP3965592A
Publication Date:
February 18, 2002
Filing Date:
February 26, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N7/08; H04N7/081; (IPC1-7): H04N7/08; H04N7/081
Domestic Patent References:
| JP1190089A |
Attorney, Agent or Firm:
Hidemori Matsukuma