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Patent Searching and Data


Title:
DISPLAY ADDRESS GENERATING DEVICE
Document Type and Number:
Japanese Patent JPS6459383
Kind Code:
A
Abstract:

PURPOSE: To simplify scrolling operation and reduce the occupation area of a circuit by using an adder instead of an LAG for 2nd and succeeding screens and finding the start addresses of the 2nd and succeeding screens by an offset method.

CONSTITUTION: The display addresses 6 of a 1st screen are generated in order by a linear address generator(LAG) 7 by setting its start address to the address of the left end of a 1st line. Once the start address of the 1st screen appears on a display address line 6, an offset 10 is added by an adder 11 to the start address of the 1st screen and the result is outputted as the start address of the 2nd screen to a display line 12. The display addresses 6 of the 1st screen from the LAG 7 and the display addresses 12 of the 2nd screen generated by the adder 11 are so switched by a selecting circuit 8 as to correspond to actual screen positions, and used as display addresses 9 to access a memory. Consequently, scrolling can be performed only by changing the start address of the 1st screen and the circuit area is reducible.


Inventors:
WAKIMOTO KINGO
Application Number:
JP21850787A
Publication Date:
March 07, 1989
Filing Date:
August 31, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G09G5/00; G09G1/00; G09G1/02; G09G5/34; (IPC1-7): G09G1/00; G09G1/02
Attorney, Agent or Firm:
Kenichi Hayase