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Title:
DISPLAY CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH02292629
Kind Code:
A
Abstract:

PURPOSE: To improve the access speed of display data and to reduce the area on a printed circuit board by making an address register and a display data buffer independent and allowing CPU and a crystal control circuit to be one chip.

CONSTITUTION: When CPU 1 generates display data to be displayed on a crystal screen, it recognizes that a status register 7 is not busy, then, a video RAM address is written in the address register 2 and display data is written in the display data buffer 6. In such a case, the register 2 and the buffer 6 independently access without through an input output buffer, and CPU 1 and the crystal control circuit are provided on the same chip. When the address of a video RAM 8 into which CPU 1 writes display data is changed at every display data, the access speed can be doubled at maximum, and the occupancy area of CPU 1 and the crystal control circuit on the printed circuit board can be reduced to about 50%.


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Inventors:
ICHIHARA TAKAO
Application Number:
JP11212389A
Publication Date:
December 04, 1990
Filing Date:
May 02, 1989
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
G06F3/153; (IPC1-7): G06F3/153
Attorney, Agent or Firm:
Namio Akio (1 person outside)



 
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