Title:
表示装置及びその設計方法
Document Type and Number:
Japanese Patent JP7117132
Kind Code:
B2
Abstract:
To realize a peripheral circuit layout simple in circuit arrangement and narrow in frame width.SOLUTION: A plurality of row circuit blocks and a plurality of column circuit blocks include a plurality of circuit block units opposed to each of a plurality of stages. Each of the plurality of circuit block units is configured by the m number of row circuit blocks and the n number of column circuit blocks which are arranged in a row along a virtual line connecting the outside apex of the opposing stage in the order that matches the order of the pixel row and the pixel column of the opposing stage. A sum total of the length in which the side opposing to the virtual line of the m number of column blocks is projected to the virtual line and the length in which the side opposing to the virtual line of the n number of column circuit blocks is projected to the virtual line is less than the length of the virtual line. A first power source line for supplying a power source to the pixel of the display area is located at the outer periphery and is arranged between the plurality of row circuit blocks and the plurality of column circuit blocks.SELECTED DRAWING: Figure 2A
Inventors:
Yoshihiro Nonaka
Yojiro Matsueda
Kenichi Takatori
Yojiro Matsueda
Kenichi Takatori
Application Number:
JP2018076768A
Publication Date:
August 12, 2022
Filing Date:
April 12, 2018
Export Citation:
Assignee:
Tenma Micro Electronics Co., Ltd.
International Classes:
G09F9/00; G09F9/30; H01L27/32; H01L51/50
Domestic Patent References:
| JP2016148843A | ||||
| JP2008292995A |
Foreign References:
| US20170116923 | ||||
| US20160225306 |
Attorney, Agent or Firm:
Fujio Patent Office