Title:
表示装置
Document Type and Number:
Japanese Patent JP7132414
Kind Code:
B2
Abstract:
A display device includes a driver circuit including a logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line which is electrically connected to the driver circuit; a pixel portion including a pixel whose display state is controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line to which reference voltage is applied; and a third transistor which is a depletion type transistor and controls electrical connection between the signal line and the reference voltage line. The first to the third transistors each include an oxide semiconductor layer including a channel formation region.
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Inventors:
Jun Oyama
Sanpei Yamazaki
Sanpei Yamazaki
Application Number:
JP2021175750A
Publication Date:
September 06, 2022
Filing Date:
October 27, 2021
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; G02F1/133; G02F1/1368; H01L27/32; H01L29/786; H01L51/50; H05B33/02; H05B33/14
Domestic Patent References:
| JP10301537A | ||||
| JP2005202209A | ||||
| JP2000148093A | ||||
| JP2006032735A |
Foreign References:
| US6307532 | ||||
| CN1933687A |