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Title:
DISPLAY MEMORY ACCESS SYSTEM
Document Type and Number:
Japanese Patent JPH06139136
Kind Code:
A
Abstract:

PURPOSE: To allow a host to access a bit map memory without being conscious of a boundary between upper and lower picture memories by preparing a register for setting up the center address of a display and an address conversion part.

CONSTITUTION: At the time of receiving an access address from an address bus 6, the address conversion part 4 compares the received address with a center address value stored in the register 3, and when the access address is less than the center address value, generates a selection signal 9 for driving an upper side memory block 1 and supplies the inputted access address to a memory block 1 as it is to execute reading/writing access operation. When the access address is more than the center address value, the conversion part 4 outputs a selection signal 10 for driving a lower side memory block 2 and supplies a difference between the inputted access address and the center address value as the address of the memory block 2 to execute access operation.


Inventors:
AOKI KINICHI
ABO KENICHI
Application Number:
JP29187492A
Publication Date:
May 20, 1994
Filing Date:
October 30, 1992
Export Citation:
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Assignee:
FUJITSU LTD
PFU LTD
International Classes:
G06F3/14; G06F3/048; G06F12/00; G06T1/60; G09G5/36; (IPC1-7): G06F12/00; G06F3/14; G06F15/64; G09G5/36
Attorney, Agent or Firm:
Fumihiro Hasegawa (1 person outside)