Title:
分散処理ノードおよび分散処理システム
Document Type and Number:
Japanese Patent JP7396463
Kind Code:
B2
Abstract:
A distributed processing node includes a computing device that calculates gradient data of a loss function from an output result obtained by inputting learning data to a learning target model, an interconnect device that aggregates gradient data between the distributed processing node and other distributed processing nodes, a computing function unit that is provided in a bus device and performs processing of gradient data from the computing device, and a DMA controller that controls DMA transfer of gradient data between the computing device and the bus device and DMA transfer of gradient data between the bus device and the interconnect device.
Inventors:
Takeshi Ito
Akiji Tanaka
Yuki Arikawa
Kazuhiko Terada
Ken Sakamoto
Akiji Tanaka
Yuki Arikawa
Kazuhiko Terada
Ken Sakamoto
Application Number:
JP2022511456A
Publication Date:
December 12, 2023
Filing Date:
April 02, 2020
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06N3/098
Foreign References:
| WO2019181374A1 | ||||
| WO2020003849A1 |
Other References:
竹本一馬 ほか,FPGAスイッチを用いたディープラーニングのパラメータ更新の検討,組込みシステムシンポジウム2017論文集,日本,一般社団法人 情報処理学会,2017年08月17日,Vol.2017,pp.13-16
Attorney, Agent or Firm:
Shigeki Yamakawa
Yuzo Koike
Masaki Yamakawa
Yasushi Motoyama
Yuzo Koike
Masaki Yamakawa
Yasushi Motoyama
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