Title:
分周補正回路、受信回路及び集積回路
Document Type and Number:
Japanese Patent JP6985579
Kind Code:
B2
Abstract:
A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second frequency division signal (CK14) which are different from each other in duty ratio; and a corrector (303) configured to generate a first output signal (CK21) having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
More Like This:
| JPS54128253 | FREQUENCY SYNTHESIZING CIRCUIT |
Inventors:
Atsushi Matsuda
Application Number:
JP2016147482A
Publication Date:
December 22, 2021
Filing Date:
July 27, 2016
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H03K23/64; H03K5/00
Domestic Patent References:
| JP201140934A | ||||
| JP2012222793A |
Foreign References:
| US20130002319 | ||||
| US20160118962 | ||||
| US20030034810 |
Attorney, Agent or Firm:
Takayoshi Kokubun
Previous Patent: LLC resonant converter with integrated magnetic circuit
Next Patent: Manufacturing method of collet and semiconductor device
Next Patent: Manufacturing method of collet and semiconductor device