To attain data transmitting operation in a wide band width.

In the controller 100 provided with bus lines consisting of a 2nd parallel data bus 107 to be a high speed parallel bus, a 1st parallel data bus 106 to be an I/O data bus and a 3rd parallel data bus 108, a direct memory access(DMA) controller circuit 103 is connected to these bus lines so that the 1st and 3rd parallel data buses 106, 108 are CODIC connected to the circuit 103. The controller 100 is also provided with a processor 105 and a memory block 104 connected to the 2nd parallel data bus 107. The circuit 103 is provided with a control & adjustor circuit 117 and an address generation circuit 116. The circuit 117 controls 1st and 2nd data buffers 109, 111 to supply data to the parallel buses and the circuit 116 generates an address string to the circuit 103.